@Jeremy Interesting.
I didnt even know Celerons supported SSE. I will have to look up its specs. I think I have idea though on the speed difference.
The ASM for both the BMax Vector and my Plain C Vector are the same there is one substantal difference. To handle the SSE intstructions my underlying data structures to handle both the SSE code and x87 code had to do some memory alignment adjustments to make the data for the vector be aligned on a 16byte boundry. I suspect with that and the size and limitations of the caching mechnisms in the Celeron architecture are cause of cache misses which are causing the additional overhead with the C Based structures.
Hmmm interesting...
Thanks for feedback
Doug
I didnt even know Celerons supported SSE. I will have to look up its specs. I think I have idea though on the speed difference.
The ASM for both the BMax Vector and my Plain C Vector are the same there is one substantal difference. To handle the SSE intstructions my underlying data structures to handle both the SSE code and x87 code had to do some memory alignment adjustments to make the data for the vector be aligned on a 16byte boundry. I suspect with that and the size and limitations of the caching mechnisms in the Celeron architecture are cause of cache misses which are causing the additional overhead with the C Based structures.
Hmmm interesting...
Thanks for feedback
Doug